The present invention relates to a display device. More specifically, the present invention relates to a display device provided with a display panel having a capacitive load such as an electroluminescent display panel (hereinafter, referred to as ELDP) or a plasma display panel (hereinafter, referred to as PDP), in which an electric field is generated to emit light, as well as a semiconductor device for driving the capacitive load.
A known display device of this type is exemplified in FIG. 10. The ELDP 1 to be driven has electrodes 8, 9 arranged in a grid at the same intervals both in the vertical and horizontal directions. Each intersection point of the electrodes 8 and 9 constitutes a pixel, which is inevitably parasitized by large capacitance 7 due to the principle of the ELDP or PDP that light is emitted by generating high electric fields between the electrodes 8 in the vertical direction and the electrodes 9 in the horizontal direction. In a driving semiconductor device 2, a few tens of high voltage CMOS (Complementary Metal Oxide Semiconductor) circuits 10 are arranged in an array to constitute output stages on a semiconductor chip. The logic state of these high voltage CMOS circuits 10 is controlled by a low voltage CMOS control circuit such as a shift register circuit or latch circuit mounted on the same chip although it is not shown in the figure. In this driving semiconductor device 2, a low potential side power terminal 11 is connected to the ground potential 12 and the power charge/discharge terminal 6 is connected to the output part of the power supply voltage control circuit 3 (composed of high voltage CMOS circuits). It is noted that the low potential side power supply of the power supply voltage control circuit 3 is connected to the ground potential 12 and the high potential side power supply is connected to a constant voltage power supply 5 of 70 V. There is provided a circuit for collecting power in the power supply voltage control circuit 3 in practice although it is not shown in the figure.
FIG. 11 shows a cross-sectional structure of an output-stage CMOS circuit in the driving semiconductor device (designated by reference numeral 2 in FIG. 10). An n-type epitaxial layer 22 is formed on a p-type semiconductor substrate 20. A high voltage n-channel MOS (hereinafter, referred to as NMOS) transistor 39 and a high voltage p-channel MOS (hereinafter, referred to as PMOS) transistor 40 are formed on this n-type epitaxial layer 22. These NMOS transistor 39 and PMOS transistor 40 are electrically isolated by a diffused p-type insulating isolation layer 21 between the surface of the n-type epitaxial layer 22 and the p-type semiconductor substrate 20. It is noted that a low voltage CMOS control circuit is also formed on the same semiconductor substrate 20 in a state that it is electrically isolated by the p-type insulating isolation layer 21 although it is not shown in the figure. The NMOS transistor 39 has a VDMOS (Vertical Double Diffused Metal Oxide Semiconductor) structure and is provided with a p-type base diffusion layer 35, gate electrode 32, source electrode 30 and drain electrode 29. It is noted that the drain current of the NMOS transistor 39 is drawn by a high-concentration n-type buried diffusion layer 23 and a high-concentration n-type drawing diffusion layer 25. 33 denotes an oxide film and 38 denotes a surface insulating film. The PMOS transistor 40 has a horizontal-type structure containing a p-type drain diffusion layer 34 for a high voltage specification and is provided with a gate electrode 31, source electrode 27 and drain electrode 26. Since the n-type epitaxial layer 22 and the p-type semiconductor substrate 20 are disposed vertically corresponding to the p-type drain diffusion layer 34 beneath this PMOS transistor 40, a parasitic bipolar transistor 4 (also shown in FIG. 10) is generated as shown in the figure. In order to keep the current amplification factor hFE of this parasitic bipolar transistor 4 low, a high-concentration n-type buried diffusion layer 23 is formed below the p-type drain diffusion layer 34 as well. Consequently, the current amplification factor hFE of the parasitic bipolar transistor 4 is reduced to about 0.05 or less.
FIGS. 12A, 12B, 12C and 12D show waveforms of respective parts in the driving semiconductor device 2. A periodic rectangular wave 50 is applied to the power charge/discharge terminal 6 by the power supply voltage control circuit 3. The voltage (see FIG. 12C) of the i-th output terminal (exemplified by the one with reference numeral 14 for convenience) out of output terminals 13, 14, 15, 16 is controlled by the periodic rectangular wave 50 (see FIG. 12A) applied to the power charge/discharge terminal 6 and the logic state 51 (see FIG. 12B) of the i-th output CMOS circuit 10 determined by image information (an H level represents an output; an L level represents a halt) and has a waveform 52 (see FIG. 12C) showing rises and falls representing integration due to the capacitive load. In FIG. 12C, 55 represents charge to the load and 56 represents discharge from the load. In FIG. 12D, 53 is a current waveform in the i-th output terminal 14. The positive direction represents output from the output terminal. 57 is charge current to the electrode 8 in the vertical direction corresponding to the i-th output terminal 14. The charge current 57 during a charge process 55 flows through the path shown as 17 in FIG. 10, that is, flows from the high-voltage constant voltage power supply 5 of 70 V through the power charge/discharge terminal 6, the PMOS transistor 40 in the ON state and the i-th output terminal 14 and charges the electrode 8 in the vertical direction. On the other hand, the discharge current 58 is returned through the path shown as 18 in FIG. 10 during a discharge process 56, that is, to the high-voltage constant voltage power supply 5 side through the path in the direction reverse to that of the charge process 55. This is because the voltage 50 (see FIG. 12A) applied to the power charge/discharge terminal 6 drops from 70 V to 0 V rapidly while the logic state 51 of the i-th output CMOS circuit is maintained at the H level. If the discharge current is returned to the high-voltage constant voltage power supply 5, the power accumulated in the capacitive component of the load can be collected. Thus, power consumption in the ELDP can be reduced. However, since a current path 61 flowing to the ground side 12 is generated by the parasitic bipolar transistor 4 during the discharge process 56, the power collection efficiency decreases. The ratio (i1/i2) of the current component i1 that can collect power by returning this discharge current to the high-voltage constant voltage power supply 5 and the current component i2 that cannot return the discharge current to the high-voltage constant voltage power supply 5, thereby being unable to collect power, is expressed by
i1/i2=1/hFE
where hFE is the current amplification factor of the parasitic bipolar transistor 4. As described above, since the current amplification factor hFE of this parasitic bipolar transistor 4 is reduced to about 0.05 or less, most of the power accumulated in the capacitive component of the load can be collected.
In the above method, however, an buried diffusion layer 23, epitaxial layer 22, insulating isolation layer 21 and the like need to be provided within the chip of the driving semiconductor device 2 to increase the power collection efficiency by reducing the current amplification factor hFE of the parasitic bipolar transistor 4. Therefore, there is a problem that the driving semiconductor device 2 to be used requires a complicated fabricating process.
It has been proposed that as shown in FIG. 13, the current flowing to the ground potential 12 is eliminated by inserting a switching element 71 between the low potential side power terminal 11 of the driving semiconductor device 2 and the ground potential 12 and keeping the switching element 71 off during the discharge process and substantially all the power charged to the capacitive load is collected irrespective of the current amplification factor hFE of the parasitic bipolar transistor 4 (Japanese Patent Laid-Open Publication HEI 10-335726). In this method, however, control of the high-voltage CMOS output transistor controlled by the low-voltage CMOS control circuit becomes unreliable because the low potential side power supply of the low-voltage CMOS control circuit is also separated from the ground potential 12 when the switching element 71 is turned off. Therefore, this method cannot be employed in practice.
Accordingly, an object of the present invention is to provide a display device provided with a display panel having a capacitive load such as an ELDP or PDP and a semiconductor device for driving the capacitive load which can reliably operate, collect substantially all the power charged in the capacitive load irrespective of the current amplification factor of a parasitic bipolar transistor and be fabricated by a simple fabricating process.
In order to achieve the above object, the display device of the present invention provides a display device comprising:
a display panel having a capacitive load, and a semiconductor device having a high potential side power terminal to which a high potential is applied, a low potential side power terminal to which a low potential is applied, a power charge/discharge terminal to which a pulsed driving waveform changing between the high potential and the low potential is applied and an output terminal to which the capacitive load is connected, the semiconductor device functioning to generate an output responsive to the driving waveform to the output terminal to thereby drive the capacitive load, wherein
the semiconductor device comprises a first p-channel MOS transistor having a source connected to the power charge/discharge terminal, a drain connected to the output terminal, a backgate connected to the high potential side power terminal, and a gate to which a first control signal indicating that the first p-channel MOS transistor should be turned on during an output period in which the capacitive load is to be charged and discharged is applied.
In the display device of the present invention, the first control signal is set at a low (L) level during the output period when the capacitive load needs to be charged and discharged. Consequently, a first p-channel MOS transistor is turned on. Therefore, the charge current flows from the power charge/discharge terminal to the capacitive load through the first p-channel MOS transistor in the ON state and the output terminal during the rise process of the driving waveform. On the other hand, the discharge current flows from the capacitive load to the power charge/discharge terminal through the output terminal and the first p-channel MOS transistor in the ON state during the fall process of the driving waveform. In the semiconductor device, for example, when a first p-channel MOS transistor is provided on a semiconductor substrate with which a low potential side power terminal is in conduction, by a common CMOS circuit fabricating process, there is generated a parasitic bipolar transistor using the source and the backgate of the first p-channel MOS transistor and the semiconductor substrate as its emitter, base and collector, respectively. However, since the potential of the power charge/discharge terminal to which the source of the first p-channel MOS transistor is connected is lower than the potential of the high potential side power terminal to which the backgate of the first p-channel MOS transistor is connected during the fall process of the driving waveform, the emitter and the base of the parasitic bipolar transistor are reverse-biased. Therefore, the discharge current is not drawn even in part to the low potential side power terminal through such a parasitic bipolar transistor. Thus, substantially all the power charged in the capacitive load is collected through the power charge/discharge terminal irrespective of the current amplification factor of the parasitic bipolar transistor. Also, since a buried diffusion layer or the like for reducing the current amplification factor of the parasitic bipolar transistor is not required inside the chip as a result, the semiconductor device can be fabricated by a simple fabricating process. Also, since the low potential side power terminal can be connected to the ground potential at all times, operation of the control circuit never becomes unreliable even in the case where a control circuit for controlling the ON/OFF state of the first p-type MOS transistor is provided on the semiconductor substrate.
In one embodiment, the semiconductor device comprises a second n-type MOS transistor having a source connected to the power charge/discharge terminal, a drain connected to the output terminal, and a gate to which a second control signal opposite in phase to the first control signal is applied.
In the display device of this embodiment, the first control signal is set at a low (L) level while the second control signal is set at a high (H) level during the output period when the capacitive load needs to be charged and discharged. Consequently, not only the first p-channel MOS transistor is turned on but also the second n-type MOS transistor in parallel with the first p-channel MOS transistor is turned on. As a result, the on-resistance of the charge/discharge path is kept low even when the potential of the power charge/discharge terminal changes depending on the driving waveform. Therefore, the power collection efficiency is increased.
In another embodiment, the semiconductor device comprises a third n-type MOS transistor having a source connected to the low potential side power terminal, a drain connected to the output terminal, and a gate to which a third control signal in the same phase with that of the first control signal is applied.
In the display device of this embodiment, the third control signal is set at a low (L) level during the output period when the capacitive load needs to be charged and discharged. Therefore, the third n-type MOS transistor is turned off and does not contribute to the charge/discharge operation through the output terminal. On the other hand, the third control signal is set at a high (H) level during the halt period when the capacitive load is not charged or discharged. Therefore, the third n-type MOS transistor is turned on and the potential of the output terminal is kept low and stable during the halt period.
In another embodiment, the first control signal and the third control signal are given by an identical signal.
In the display device of this embodiment, since the same signal is used as the first control signal and the third control signal, control becomes easy and the configuration of the control circuit is simplified.